Senseeker Sponsors UCSB Engineering Capstone VCO ADC Project

Sean McCotter (Analog and Mixed Signal IC Design Engineer) & Jeremiah Ford (Mixed Signal IC Design Engineer)




For the second year in a row, Senseeker has been proud to sponsor a team of burgeoning engineers at the University of California, Santa Barbara through the UCSB Engineering Capstone Program. In this program, both industry partners and local research labs create interesting and challenging project ideas for groups of seniors in the College of Engineering to make a reality. This puts students into an environment where they must begin to make their own decisions as engineers. Their work in these projects forms the cornerstone of their educational journey.

Senseeker tasked our student team with designing a Voltage-Controlled Oscillator based Analog-to-Digital Converter (VCO ADC). This project blended together many disciplines within electrical engineering, requiring the students to design a linear analog VCO front-end, a digital interface to monitor the VCO, and a digital decimation filter including correction for VCO non-linearity. Senseeker's goal with the project was to expose the students to a real-world design flow for high performance circuit design, starting from derivation of block specifications and moving all the way through lab testing.

The five students who volunteered for this project were Kailin Kozacko, Jason Ngo, Shuhan Mao, Zexi Liu and Isaac Bao. In September 2020, they began their quest to build a VCO ADC. The team started from the ground up researching and discussing designs that would work for their set of design constraints. At the Capstone Expo in June, they presented SensrLink, the final iteration of their VCO ADC design.

For maximum sensor compatibility, SensrLink uses a low noise, variable gain-and-offset analog front-end (AFE) to remap an arbitrary sensor input voltage range to the VCO ADC full scale range (FSR). The output of the AFE is then buffered into a linear transconductance stage, producing an output current proportional to the input voltage. The output current is used to bias a 11-stage current starved inverter VCO, forcing the ring oscillator to oscillate at a frequency proportional to the bias current. The VCO node voltages are sensed, level shifted, and buffered into an FPGA, which processes the sampled states of the VCO. The FPGA oversamples the VCO state and calculates the number of edge transitions since the last sampled state. These signals are then driven out to a digital logic analyzer, which saves the data for post-processing in MATLAB. MATLAB scripts decimate the output data while applying a filter to undo the characterized nonlinearity of the VCO. To complete their design, the team fabricated a PCB that integrated the VCO, the associated VCO bias circuits, and the digital output buffers and level shifters. The final SensrLink design was able to achieve an ENOB of over 9 bits at an input sample rate of 10 kS/s.

The entire Senseeker team was thoroughly impressed with the SensrLink Capstone team's perseverance and critical thinking skills as they weathered through numerous challenges imposed by both their ambitious design goal and the global pandemic. We really enjoyed working closely with the students on the team and appreciate their hard work, as well as the support of the UCSB faculty to continue this fantastic program!


About Senseeker Engineering

Senseeker is a US owned transducer IC and cryogenic test solutions company that specializes in the design of state-of-the-art digital imaging sensors, cryogenic test equipment, electronics and software. Senseeker's products and IP enable FPA developers to produce world class infrared image sensing solutions. Read more at


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Insight # IS-20210614-01